1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more specifically to techniques for aligning contacts when forming interconnect for integrated circuit devices.
2. Description of the Prior Art
As feature sizes and device sizes shrink for integrated circuits, relative alignment between interconnect layers becomes of critical importance. Misalignment can severely impact the functionality of a device. Misalignment beyond certain minimum tolerances can render a device partly or wholly non-operative.
To insure that contacts between interconnect layers are made properly even if a slight misalignment occurs during masking steps, extra space is usually included in a design around contacts and other conductive features. This extra retained space is known as enclosure. Enclosure sizes of up to a few tenths of a micron are typical for 0.5 to 1.0 micron feature sizes.
Enclosure requirements are not consistent with the continued shrinkage of devices. Enclosure is not related to device functionality, but is used only to ensure that misalignment errors don't cause problems with the device. When designing devices having minimum feature and device sizes, minimizing enclosure requirements can significantly impact the overall device size.
Self-alignment techniques are generally known in the art, and it is known that their use helps minimize enclosure requirements. However, the use of self-alignment techniques has been somewhat limited by device designs in current use. It would be desirable to provide a technique for fabricating integrated circuit devices which increase the number of self-aligned steps, thereby reducing enclosure requirements for the device.
High density dynamic random access memory (DRAM) devices have regular layouts which allow for small device sizes. Obtaining minimum cell sizes is very important to the design of high density DRAMs, such as 16 megabit and 64 megabit devices. The area penalty caused by enclosure requirements can significantly affect overall chip size, since the individual cell sizes are so small for such high density devices.
It would therefore be desirable to provide a cell layout and fabrication technique for high density DRAMs which is as small as possible. Such a fabrication technique preferably includes self-aligned structures and process steps when possible to minimize total cell area. It is further desirable for such a technique to be compatible with process flows currently in standard use.